Flash memory devices store information with high density on Flash cells with ever smaller dimensions. In addition. Multi-Level Cells (MLC) store several bits per cell by setting the amount of charge in a cell. Flash devices are organized into (physical) pages. Each page contains a section allocated for data (512 bytes-8 Kbytes and expected larger in the future) and a small amount of spare bytes (64-512 or more bytes for every page) containing redundancy and metadata. The redundancy bytes are used to store error correcting information, for correcting errors which may have occurred during NAND flash lifetime and the page Read process. Each Program operation is performed on an entire page. A number of pages are grouped together to form an Erase unit (erase unit). A page cannot be erased unless the entire erase unit which contains it is erased.
Common applications of Flash devices are Secure Digital (SD) cards or Multi Media (MMC) cards or such embedded devices (eSD and eMMC). An SD card may typically contain Flash devices and a memory controller. The controller translates commands coming in through the SD interface into actions (Read/Write/Erase) on the Flash devices. The most common SD commands may be Read and Write commands of one or more sectors. Where a sector may be, but is not limited to, a sequence of 512 bytes. The Read or Write commands may be of a single sector or multiple sectors. These commands may refer to logical addresses. These addresses may then be redirected to new addresses on the Flash memory which need not directly correspond to the logical addresses that might be referenced by the Read or Write commands. This is due to memory management that may be carried out by the memory controller in order to support several features such as wear-leveling, bad block management, firmware code and data, error-correction, and others. The erase function is performed on an entire erase unit. Because of this functionality, before the data of a certain block may be replaced such as during a write function, the new data must be written in an alternative location before an erase can occur, to preserve the integrity of the stored data.
Due to the small dimensions of a typical SD card and the price limitations, the controller may typically have only a small RAM available for storage. The small size of the RAM memory limits the type of memory management which may be carried out by the controller with regard to the data stored in the flash memory and received from the interface. The controller may typically manage the memory at the erase unit level, because managing data of small particle sizes becomes difficult. That is, the logical memory space may be divided into units of memory contained within a single erase unit or some constant multiple of erase units, such that all logical sector addresses that fall in boundaries of logical addresses of an erase block size will be mapped to the same erase block. This requires that the controller may only hold an erase block allocation map rather than a map that is capable of mapping to the location of individual data sectors or data particles of page size. This may allow the controller to use a smaller amount of the RAM memory for the purpose of managing the links between logical addresses and the location of the data sectors that have been written to the flash memory unit.
This type of management has the drawback that for writing random access data sector to memory or other memory units smaller than an erase unit, erase units must be frequently rewritten. Because of the characteristics of flash memory, each new piece of information is written into an empty page. In flash memory a page may not be rewritten before the entire erase unit is erased first.
If a portion of the memory unit contained within an erase unit is rewritten, it is first written into a freshly allocated, erased erase unit. The remaining, unmodified, contents of the erase unit may then be copied into the new erase unit and the former erase-block may be declared as free and may be further erased. This operation may be referred to as “sealing” or “merging”. The operation involves collecting the most recent data of a logical block and then merging it with the rest of the block data in a single erase unit. Thus, even if a single sector from an erase unit is rewritten, a complete erase unit would be rewritten. This may result in causing a significant degradation in the average write speed. It may also impose a significant delay in the response time between random write sector operations. It also may cause undeliverable flash P/E (program/erase) cycling, which may be very significant in new generations of NAND flash where the number of P/E cycles is limited to a few thousand.